We provide the following training

    Memory Design/Margining/Characterization [15 Weeks]

    We provide world class training for Memory design which includes SRAM bit cell working and sizing, SRAM architecture, Pulse shaping, Clock generator, Row and Column Decoder , pre decoders and WL driver Self timing path, Memory Margining, Sense amp offset analysis, Bitcell SNM/ADM/Writability analysis, Read and Write Margins, Designing Write assist techniques, Scan chain and redundancy circuit design and Characterization.

    Standard Cell Design and Characterization [10 Weeks]

    We provide world class training for Standard Cell design which includes Finding n2p ratio at different corners and voltage, Basic Gates Functionality and design requirements, Standard cell characterization - Timing Arcs/Timing Sense/Power/Leakage/Input Cap/Noise/IV curve Characterization , CCS char , OCV characterization.

    Physical Design and STA [16 Weeks]

    We provide world class training using Cadence flows for physical design and STA which includes Floor planning, PG Planning, Place, Optimization for Timing and Power, Clock Tree Synthesis, Routing, Post Route Optimization, Low Power Expertise(Clock Gating, Multi-Vt, Voltage Islands, Power Gating),EM & IR drop analysis, Timing Closure and Static Timing Analysis and Physical Verification (DRC/ERC/LVS).